Zero hardware knowledge → Virtex-7 deployment

Learn FPGAs the way you'd actually need to, to ship a CNN descriptor onto real silicon.

No HLS, no Vivado, no AXI on day one. Every phase below is a wire you need to understand before the next one makes sense.

A roadmap for going from zero hardware knowledge to Virtex-7 deployment — CNN feature extractor deployment for a real-time image matching pipeline, targeting inference under 10 seconds.

The signal chain — 13 phases, in order

PHASE 00 What even is an FPGA? 1–2 days

A CPU runs instructions one at a time. An FPGA becomes the circuit you need.

PHASE 01 Number systems & binary 2–3 days

Every CNN weight and pixel value eventually becomes a pattern of on/off signals.

PHASE 02 Basic logic circuits 1 week

Everything — adders, memory, your whole CNN pipeline — is gates wired together.

PHASE 03 Timing — why hardware breaks silently 2–3 days

Simulation won't warn you. Only real hardware misbehaves when timing is violated.

PHASE 04 Verilog — describing circuits in text 2–3 weeks

You're not writing instructions. You're describing wires and boxes that all exist at once.

PHASE 05 FPGA-specific building blocks 1 week

Learn the pre-built resources inside a real chip so you're not reinventing everything from raw gates.

PHASE 06 Fixed-point arithmetic & quantization 1 week

FPGAs are bad at decimals. You fake them with integers and just remember where the point is.

PHASE 07 Streaming data / line buffers 1 week, hands-on

You can't fit a whole image in the FPGA. You stream pixels and remember just a sliding window.

PHASE 08 CNN layer in hardware 2 weeks

Line buffer + DSP48 MACs + fixed-point math + a free comparator = one conv layer.

PHASE 09 The toolchain (Vivado) — now it clicks 1–2 weeks

Vivado just takes your Verilog description and turns it into a real, working chip configuration.

PHASE 10 HLS — writing hardware in C++ 1–2 weeks

Write something that looks like C++, get real Verilog circuitry out the other end.

PHASE 11 AXI & integration 1 week

A standard plug shape so your CNN accelerator can talk to the ARM processor next to it.

PHASE 12 On-board testing & deployment ongoing

Simulation proves your logic is right. Only the real chip can prove your timing and wiring are.

Core concepts you'll lean on constantly

HW-01

LUT

The general-purpose programmable logic block an FPGA is built from.

HW-02

Flip-flop

1-bit memory that updates only on the clock edge — the atom of hardware memory.

HW-03

BRAM

On-chip memory blocks — where CNN weights and feature maps will live.

HW-04

DSP48

Dedicated multiply-accumulate hardware — the physical engine behind every convolution.

NUM-01

Two's complement

How negative CNN weights are actually stored in binary.

NUM-02

Fixed-point (Q-format)

How FPGAs fake decimal points using plain integers.

HDL-01

Combinational vs sequential

always @(*) (instant) vs always @(posedge clk) (clocked) — the #1 beginner trap.

HDL-02

Blocking vs non-blocking

= executes in order; <= updates all together at the clock edge.

ARCH-01

Line buffer

Streams an image row-by-row, storing only the rows needed for the current sliding window.

ARCH-02

Pipelining

Breaking a long computation into stages so one result comes out every clock tick.

TIME-01

Critical path

The slowest chain of logic between two flip-flops — sets your max clock speed.

SYS-01

AXI

The standard interface convention connecting your CNN core to the ARM processor.