Basic logic circuits

Now that you know numbers are just patterns of on/off, this phase answers the next question: how does hardware actually do something with those patterns — how does it add, compare, or store them? The answer is that everything, no matter how complex, is built from a tiny handful of dead-simple building blocks called logic gates. This phase is about seeing, concretely, how a pile of gates becomes an adder, then a memory cell, then eventually your whole CNN pipeline.

There are really only a few gates you need: AND, OR, NOT, and XOR. AND: output is 1 only if both inputs are 1 (like two switches in series — both must close for current to flow). OR: output is 1 if either input is 1 (two switches in parallel). NOT: flips the input. XOR: output is 1 if the inputs are different from each other — this one turns out to be the secret ingredient of an adder circuit. For now, treat these as black boxes with a truth table; you don't need transistor physics.

Combinational circuits have no memory — output depends only on the current inputs. An adder is built from XOR gates (the sum bit) and AND gates (the carry bit) chained together — a "full adder" adds two bits plus a carry-in, and you chain many together to add multi-bit numbers. This is literally how your accumulator circuit for CNN convolution sums will work later. A multiplexer (mux) is a hardware "switch statement" — given a selector, it picks one of several inputs to pass through. You'll use these constantly, e.g. to select which pixel enters your line buffer, or which weight gets loaded. A comparator outputs whether A > B, A = B, or A < B — this is exactly what implements ReLU later: "is the input negative? if so, output 0."

Sequential circuits have memory. Combinational circuits alone can't remember anything — as soon as inputs change, outputs change instantly. But your CNN pipeline needs to hold values between clock ticks (weights, partial sums, line buffer contents). The single most important building block here is the D flip-flop: a 1-bit memory cell that, on every clock edge, "grabs" whatever value is on its input and holds it steady until the next clock edge, ignoring any changes in between. Every register, every line buffer row, every pipeline stage in your entire FPGA design is fundamentally built from flip-flops.

A register is just a bank of flip-flops side by side, holding a multi-bit value (e.g. an 8-bit weight) instead of just 1 bit. A counter is a register that increments itself each clock tick — useful for tracking which pixel or row you're currently streaming in. A shift register is a chain of flip-flops where data moves one position over each clock tick — this is the literal hardware basis of your line buffer in Phase 7, where pixels shift through a chain of storage as the image streams in.

None of the sequential circuits above would make sense without a clock — a steady, repeating on/off pulse (like a metronome) that tells every flip-flop "now is the moment to update." Without this synchronized heartbeat, different parts of the circuit would update at unpredictable times relative to each other, causing chaos. Every FPGA design from here forward is built around this rhythm: on each clock edge, flip-flops grab new values; between edges, combinational logic (adders, comparators) settles into its new output, ready to be captured on the next edge.