FPGA-specific building blocks

Now that you know generic digital logic, it's time to learn what specific hardware resources actually live inside a Virtex-7 chip, so you're using it efficiently instead of fighting it by rebuilding everything from raw LUTs when dedicated hardware already exists for the job.

LUT (Look-Up Table) — a tiny programmable "if this input pattern, output that" table; general-purpose logic, used for control logic and glue between bigger blocks. Flip-flop — the 1-bit memory cell from Phase 2, present throughout the fabric, wired into every register you instantiate. BRAM (Block RAM) — small, fast, dedicated on-chip memory blocks, separate from the LUT fabric; this is where you'll store CNN weights and intermediate feature maps, because it's far more area-efficient than building memory out of raw flip-flops. DSP48 slice — a hardware multiply-accumulate unit, purpose-built for exactly what a CNN convolution needs: multiply two numbers and add the result to a running sum, all in dedicated silicon rather than LUT-built logic.

The reason this distinction matters practically: every one of these four resource types is finite on the chip. A Virtex-7 has a fixed count of LUTs, flip-flops, BRAM blocks, and DSP48 slices. Xilinx's synthesis and implementation tools try to automatically map your Verilog onto the right resource type — but only if you write the RTL in a pattern the tool recognizes. A convolution accumulator written carelessly might get mapped onto slow LUT-based logic instead of a DSP48, silently costing you both speed and chip area.