A standard plug shape so your CNN accelerator can talk to the ARM processor next to it.
AXI is just a standard "plug shape" — a common wiring convention so any hardware block (your CNN accelerator) can talk to the ARM processor sitting next to it on the same chip, the same way USB is a standard plug shape for any peripheral you connect to a laptop, regardless of who manufactured it.
AXI4-Lite is the simple version: a register-based interface used to configure hardware from the host processor — think "start," "done," "image base address" as a handful of readable/writable registers your ARM code pokes and reads. AXI4 (full) supports burst transfers, needed to efficiently move large image tiles or DEM patches from external DRAM into on-chip BRAM — without burst capability, image loading alone can quietly eat your entire 10-second latency budget before your CNN even starts computing.
The core mechanism underneath both is the valid/ready handshake — a simple signaling pattern that lets two modules running at different paces exchange data safely: the sender raises "valid" when data is ready to send, the receiver raises "ready" when it can accept it, and a transfer only happens on a clock edge where both are high simultaneously. This pattern shows up constantly once you start integrating multiple pipeline stages together.
This is exactly the reusable skeleton work already assigned and kept running regardless of which kernel (ICP or CNN) sits on top — the AXI-Lite/DMA/driver plumbing doesn't change based on what algorithm is inside the accelerator, which is why it was explicitly kept as-is during the pivot.