Write something that looks like C++, get real Verilog circuitry out the other end.
HLS (High-Level Synthesis) lets you write code that looks like C++ and have a tool automatically turn it into Verilog circuitry, using "pragmas" — special structured comments — to hint how much to parallelize or pipeline. It's meaningfully faster to use than hand-writing Verilog for something the size of a full CNN, but it only makes sense to learn now, after you already understand what's actually being generated underneath — otherwise the pragmas are just magic incantations you're copying without understanding why they help or hurt.
This is directly the tool being used right now for the conv+ReLU layer task on your project. Writing the layer in HLS with pragmas like #pragma HLS PIPELINE, and understanding that a for-loop over 9 taps with the right pragma becomes 9 parallel DSP48 multiplies rather than 9 sequential ones, is the entire payoff of having done Phases 0–9 first — without that grounding, you'd have no way to sanity-check whether the tool actually did what you intended.
This is directly the tool used for the conv+ReLU layer task right now: writing the layer in HLS with pragmas like PIPELINE, and understanding that a for-loop over 9 taps becomes 9 parallel DSP48 multiplies rather than 9 sequential ones, is the entire value of having done Phases 0–9 first.