Vivado just takes your Verilog description and turns it into a real, working chip configuration.
Now that you understand what circuits actually are, Vivado stops being a mysterious black box. It's simply the software that takes your Verilog description and (a) checks it makes logical sense, (b) turns it into a physical layout on the actual chip, (c) checks that layout is fast enough for your target clock, and (d) packages it into a bitstream file the FPGA loads at power-on.
Run each step manually at least once — Simulation → Synthesis → Implementation (place & route) → Timing report → Bitstream — so you understand what each stage actually produces and what its specific failure modes look like, rather than relying on a single push-button "run everything" flow that hides exactly where and why something went wrong.
Two report numbers matter more than anything else once you get here: WNS (Worst Negative Slack — must be ≥ 0 for timing closure; a negative number means some path in your design is too slow for the clock you asked for) and resource utilization percentages (BRAM and DSP48 usage are the typical bottlenecks for a CNN pipeline like yours, since both are finite and shared across your whole design).
This is exactly the flow anyone on an FPGA-deployment track ends up learning hands-on — the tool mechanics are fully reusable no matter which algorithm (a classical registration method like ICP, or a CNN descriptor) ends up going through it.