Line buffer + DSP48 MACs + fixed-point math + a free comparator = one conv layer.
This phase is where every previous phase gets combined into one working circuit. A convolution layer is: the line buffer (Phase 7) feeds a sliding window into several DSP48 multiply-accumulates (Phase 5) using fixed-point math (Phase 6), followed by ReLU — a single "if negative, output 0" comparator, which is nearly free in hardware compared to the multiply-accumulate stage that dominates both timing and resource usage.
The goal at this stage is one working INT8 3×3 conv + ReLU layer in Verilog (or HLS), using dummy weights — real trained weights aren't necessary yet, because the point of this stage is validating that the pattern works correctly, cycle-for-cycle, against a Python fixed-point simulation of the same layer. Getting the plumbing right with placeholder numbers now means when real weights arrive, it's a drop-in swap rather than a redesign.
This is exactly the kind of stand-in task assigned when an FPGA track is pointed toward CNN-relevant hardware rather than a different algorithm — the dummy-weight conv+ReLU layer teaches the precise pattern that will later be reused with real trained weights once the CNN training side finishes. Verifying output cycle-by-cycle (not just "final answer matches") matters because it catches timing and pipelining bugs that a final-value-only check would miss entirely.
This is exactly the stand-in task for the CNN pivot: the dummy-weight conv+ReLU layer teaches the precise pattern that will later be reused with real trained weights once the CNN training side is finished — swapping in real weights becomes a drop-in change rather than a redesign.